The present invention relates to a semiconductor memory device, and more particularly to a delay locked loop (DLL) circuit for controlling an internal operation to output data in synchronization with a system clock when an external command is inputted to a semiconductor memory device.
In a system with a variety of semiconductor devices, a semiconductor memory device serves as data storage. The semiconductor memory device outputs data corresponding to addresses received from a data processor, e.g., a central processing unit (CPU), or stores data received from the data processor into memory cells selected by addresses.
As the operating speed of the system is increasing and semiconductor integrated circuit technologies are advanced, semiconductor memory devices are required to input and output data at higher speed. To meet this requirement, a synchronous semiconductor memory device was developed. The synchronous semiconductor memory device is designed to input or output data in synchronization with a system clock received from an outside. However, since even the synchronous semiconductor memory device could not meet the required data input/output speed, a double data rate (DDR) synchronous semiconductor memory device was developed. The DDR synchronous semiconductor memory device is designed to output or input data at falling edges and rising edges of the system clock.
The DDR synchronous semiconductor memory device must be able to process two data during one cycle of the system clock so as to input or output data at both of the falling edge and the rising edge of the system clock. Specifically, the DDR synchronous semiconductor memory device should output data exactly in synchronization with the rising edge and the falling edge of the system clock. To this end, a data output circuit of the DDR synchronous semiconductor memory device controls an internal output and transfer timing of data so as to output data in synchronization with rising and falling edges of the system clock.
In a read operation, a semiconductor memory device should output data in response to an external read command after a predetermined periods of a system clock elapse from the input of the external read command. At this point, it is a column address strobe (CAS) latency that determines a data output timing. Generally, a semiconductor memory device supports a plurality of CAS latencies that can be adjusted according to operation environments of the semiconductor memory device. The CAS latencies are stored in a mode register set (MRS) of the semiconductor memory device. When the external read command is inputted, the semiconductor memory device determines the data output timing according to the CAS latencies set in the MRS using the system clock.
The system clock inputted to the semiconductor memory device inevitably has a predetermined delay time until it arrives at a data output circuit because it passes through a clock input buffer, a transfer line, and so on. Accordingly, if the data output circuit outputs data in synchronization with the delayed system clock, an external device will receive data that are not synchronized with rising edges and falling edges of the system clock. To solve this problem, the semiconductor memory device uses a delay locked loop (DLL) circuit. The DLL circuit compensates for the delay caused by internal circuits until the system clock inputted to the semiconductor memory device is transferred to the data output circuit.
To output data exactly after a CAS latency in response to the external command, the semiconductor memory device includes a data output controller to determine a data output timing by using a DLL clock outputted from a DLL circuit and a CAS latency set in an MRS.
FIG. 1 is a block diagram of a data output control circuit of a conventional semiconductor memory device.
Referring to FIG. 1, the data output control circuit includes an output control signal generator 120, an output enable signal generator 140, delays 110A and 1108, a strobe generator 160, a driver controller 170, and a latch controller 180.
In a read operation, data outputted from a unit cell passes through a global line and is aligned in a pipeline latch. The data is applied to an output driver and is finally outputted to the outside in response to rising and falling data output signals. Since the read command is inputted, the semiconductor memory device outputs the data corresponding to the read command after the CAS latency. A data output controller is used for controlling the data output timing. The data output controller outputs an output enable signal, rising and falling data output signals RCLKD0 and FCLKD0, a latch enable signal POUT, and a driver enable signal DOUTOFF. A read detection pulse CASP6RD is activated in response to a read command, and the output enable signal is activated in response to the read detection pulse CASP6RD. The rising and falling data output signals RCLKD0 and FCLKD0 indicate data output timings corresponding to the CAS latencies. The latch enable signal POUT and the driver enable signal DOUTOFF are used for controlling the pipeline latch and the output driver that the data pass through before being outputted to the outside. In particular, since the data received form the global line is transferred to the output driver through the pipeline latch, the pipeline latch should be enabled prior to the output driver so as to completely transfer the data to the output driver. The rising and falling data output signals RCLKD0 and FCLKD0 indicating output timings of data outputted in synchronization with the rising and falling edges of the system clock CLK can also be applied to the generation of a data strobe signal (DQS).
When the output control signal generator 120 receives the read detection pulse CASP6RD indicating the input of the external read command RD, it outputs a plurality of output source signals OE2, OE25, OE3 and OE35 having phase difference corresponding to half period of the system clock. The plurality of output source signals OE2, OE25, OE3 and OE35 are used to output rising and falling enable signals ROUTEN and FOUTEN to the strobe generator 160, the driver controller 170, and the latch controller 180, based on CAS latencies CD and CIA set in the MRS. The plurality of output source signals OE2, OE25, OE3 and OE35 are selected according to the CAS latency and corresponding to each of the rising and falling edges of the system clock. Accordingly, the number of the output source signals OE2, OE25, OE3 and OE35 is two times the number of the CAS latencies (CL3 and CL4, in this example)
The latch controller 180 outputs the latch enable signal POUT in response to the rising and falling enable signals ROUTEN and FOUTEN and the DLL clocks RCLKDLL and FCLKDLL outputted from the DLL circuit. The latch enable signal POUT enables the data output of the pipe line latch, which is a stage prior to the data output driver. In addition, in response to the rising and falling enable signals ROUTEN and FOUTEN and the DLL clocks RCLKDLL and FCLKDLL, the driver controller 170 outputs the driver enable signal DOUTOFF for controlling a timing when data is outputted from the data output driver, and the strobe generator 160 outputs the rising and falling data output signals RCLKD0 and FCLKD0 for controlling a timing when data is finally outputted through a data pad. In order to sequentially transfer data to be outputted to the outside, the latch enable signal POUT should be activated one cycle of the system clock earlier than the CAS latency CL, and the driver enable signal DOUTOFF and the rising and falling data output signals RCLKD0 and FCLKD0 should be activated half the cycle of the system clock earlier than the CAS latency CL. Due to the different activation timing of the signals, the rising and falling enable signals ROUTEN and FOUTEN are delayed through the delays 110A and 110B by a predetermined time and then are applied to the strobe generator 160 and the driver controller 170.
That is, in order to output data after the CAS latency in response to the external read command, the latch enable signal POUT, the driver enable signal DOUTOFF, and the rising and falling data output signals RCLKD0 and FCLKD0 must be able to exactly activated in sequence at a preset timing. To this end, as illustrated in FIG. 1, the conventional semiconductor memory device is configured to control the activation timings of the signals by using the delays 110A and 1108.
FIG. 2A is a circuit diagram of the output enable signal generator 140 illustrated in FIG. 1.
Referring to FIG. 2A, the output enable signal generator 140 includes a rising signal generating unit 142 and a falling signal generating unit 144. Each of the rising signal generating unit 142 and the falling signal generating unit 144 is implemented with transfer gates and a plurality of inverters.
Upon operation of the output enable signal generator 140, the rising signal generating unit 142 receives the plurality of output source signals OE2 and OE3 activated in synchronized with rising edges of a system clock, and selectively transfers them according to the CAS latencies CL3 and CL4. In a similar manner, the falling signal generating unit 144 receives the plurality of output source signals OE25 and OE35 activated in synchronization with falling edges of the system clock, and selectively transfers them according to the CAS latencies CL3 and CL4.
FIG. 2B is a circuit diagram of the strobe generator 160 illustrated in FIG. 1.
Referring to FIG. 2B, the strobe generator 160 includes a rising strobe generating unit 162 configured to generate the rising data output signal RCLKD0 in synchronization with the rising edge of the system clock. Although not shown, the strobe generator 160 also includes a falling strobe generating unit configured to generate the falling data output signal FCLKD0 in synchronization with the falling edge of the system clock. Specifically, the rising strobe generating unit 162 includes a NAND gate and an inverter.
The strobe generator 160 performs an AND operation on a delayed rising enable signal ROUTEND by the delay 110A and the DLL clock RCLKDLL to output the rising data output signal RCLKD0 corresponding to the rising edge of the system clock. Although not shown, the strobe generator 160 performs an AND operation on a delayed falling enable signal FOUTEND by the delay 110A and the DLL clock FCLKDLL to output the falling data output signal FCLKD0 corresponding to the falling edge of the system clock.
FIG. 3 is a timing diagram illustrating the operation of the data output control circuit of FIG. 1.
As illustrated in FIG. 3, in order to generate the rising data output signal RCLKD0 for normal data output, the delayed rising enable signal ROUTEND outputted from the delay 110A should be activated prior to the rising edge of the DLL clock RCLKDLL corresponding to the data output timing. That is, the activation timing of the delayed rising enable signal ROUTEND should be in a logic low period (deactivation period) defined prior to the rising edge of the DLL clock RCLKDLL. This is because the activation period ranging from the rising edge to the falling edge of the DLL clock RCLKDLL may be the activation period of the rising data output signal RCLKD0 and the data can be normally outputted.
If the phase of the delayed rising enable signal ROUTEND outputted from the delay 110A is adjusted to start from the center of the logic low period of the DLL clock RCLKDLL, the operation margin corresponding to ¼ period of the system clock can be obtained. Thus, it does not matter when the semiconductor memory device uses a system clock with a low frequency. However, due to the change of operation environments of the semiconductor memory device, such as voltage level, temperature, and process, the delay amount of the delays 110A and 110B using a plurality of delay elements may be changed.
Furthermore, when the semiconductor memory device uses a system clock with a high frequency, the operation margin corresponding to ¼ period of the system clock may be insufficient. Referring to FIG. 3, when the delay amount of the delay 110A is not typical, that is, when the delay amount of the delays 110A and 110B decreases (a FAST case), or the delay amount of the delays 110A and 110B increases (a SLOW case), the activation period of the rising data output signal RCLKD0 is not normally ensured. In this case, the valid window of data outputted in synchronization with the rising data output signal RCLKD0 is also reduced and it is uncertain whether data is normally outputted, thus degrading the operation reliability of the semiconductor memory device.